HMC704LP4E【PDF 37/44 页】IC FRACT-N PLL 16BIT 24QFN

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Sheet目录1996

33页 34页 35页 36页 [37页]38页 39页 40页 41页

5 - 42

HMC704LP4E

v03.1211

8 GHz fractionaL-n PLL

For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824

Phone: 978-250-3343

Fax: 978-250-3373

Order On-line at www.hittite.com

Application Support: Phone: 978-250-3343 or apps@hittite.com

table 23. reg 0ah auxSPi trigger register

BIT

TYPE

NAME

DEFLT

DEsCRIPTION

[11:0]

R/W

Reserved

[12]

R/W

No AuxsPI Trigger

No AuxsPI trigger on Reg5 Write

[15:13]

R/W

reserved

Reserved

[16]

R/W

Force RDivider Bypass

Force the R Divider Bypass, ignore Reg03

table 24. reg 0Bh PD register

BIT

TYPE

NAME

DEFLT

DEsCRIPTION

[2:0]

R/W

pd_del_sel

sets PD reset path delay

[3]

R/W

short PD Inputs

shorts the inputs to the Phase Detector - Test Only

[4]

R/W

pd_Invert

Inverts the PD polarity

0 - Use with a positive tuning slope VCO and passive loop filter

(default).

1 - Use with a negative slope VCO or with an inverting active loop

filter with a positive slope VCO.

[5]

R/W

pd_up_en

Enables the PD UP output, see also Reg0B[9]

[6]

R/W

pd_dn_en

enables the PD DN output, see also Reg0B[9]

[8:7]

R/W

CsP Mode

Cycle slip Prevention Mode

0: CsP Disabled

1: CP Gain increased if Phase Error > 2 nsec

2: CP Gain increased if Phase Error > 4 nsec

3: CP Gain increased if Phase Error > 6 nsec

[9]

R/W

Force CP UP

Forces CP UP output on - Use for Test only

[10]

R/W

Force CP DN

Forces CP DN output on - Use for Test only

[11]

R/W

Force CP MId Rail

Force CP MId Rail - Use for Test only

[14:12]

R/W

Ps Bias

Prescaler Bias

0: Nominal

1: +20% RF Buffer

2: +25% Rsync

3: +50%

[16:15]

R/W

CP Internal OpAmp Bias

[18:17]

R/W

MCounter Clock Gating

0: MCounter Off for N<32

1: N<128

2: N< 1023

3: All Clocks ON

[19]

R/W

Reserved

[21:20]

R/W

Divider Pulse Width

0: shortest, ... 3: Longest

[23:22]

R/W

Reserved

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